Project History and Previous Research
The iiQueue
The
Illinois Input Queue (iiQueue)
is a generalized input queuing module that
implements features of the 3DQ to buffer cells at the input of an ATM
switch.
It implements the
Three Dimensional Queue (3DQ) system
to buffers cells according to their
output destination port, their flow, and their priority.
An initial hardware system was prototyped using Field Programmable
Gate Arrays (FPGAs) devices and Static Random Access Memory (SRAM).
The iiQueue hardware was prototyped on six-layer,
33cm x 20cm Printed Circuit Board (PCB).
A photograph of the iiQueue is shown in
below.
Photograph of the iiQueue
Initial Integration of WUGS and iiQueue
An first prototype of the combined system
was implemented by connecting the existing iiQueue to the
Washington
University Gigabit Switch (WUGS)
using a conversion circuits.
These circuits are needed because the iiQueue's
switch and line card connectors used 40-pin standoffs, while the WUGS
uses AMP 536255-6 and 149011-6 components.
First Prototype Integration of WUGS and iiQueue
A diagram of the combined system is shown above.
The iiQueue fits between the line card and the WUGS switch.
Incoming cells are first received by the line card.
They are next buffered by the iiQueue.
They are finally passed to the WUGS for switching to their output port.
The first operation of the combined WU-iiQueue system
occured just recently on 8/4/98. Photographs of this
system are shown below:
