Integration of iiQueue and WUGS
John W. Lockwood
lockwood@ipoint.vlsi.uiuc.edu
iPOINT Research Group
Department of Electrical and Computer Engineering
University of
Illinois at Urbana--Champaign
405 N. Mathews Ave.
Urbana, IL 61801
Network Development Group
National
Center for Supercomputing Applications (NCSA)
605 East Springfield Ave.
Champaign, IL 61820
| The Washington University Gigabit Switch (WUGS) provides a scalable architecture that is likely to be used for future high-speed networks. Quality of Service (QoS) can be supported on this switch by interfacing hardware at the edge of the switch. The 3DQ, designed at the University of Illinois, is an intelligent module which provides QoS by organizing cells according to their priority, destination, and virtual circuit. A functional prototype of this module, called the Illinois Input Queue (iiQueue), has been prototyped using a printed circuit board, field programmable gate arrays, and SRAM Memory. For this research, we propose to integrate the WUGS and the iiQueue to build a highly scalable ATM switch which supports per-virtual circuit QoS. |
The Washington University Gigabit Switch (WUGS) architecture is optimal in the way that it scales the hardware for additional ports. As such, the WUGS architecture is likely to be used in future high-speed networks. To support Quality of Service, however, the switch must be augmented with additional hardware that provides congestion control and per-virtual circuit queueing.
As a part of the Illinois Pulsar-based Optical Interconnect (iPOINT) testbed, an intelligent queue module has been developed that uses pointers and a linked list of memory to organize ATM cells into multiple queues. This design, called the three dimensional queue (3DQ), processes cells according to priority, destination, and virtual circuit. A functional prototype of this queue, called the Illinois Input Queue (iiQueue), has been prototyped using a printed circuit board, field programmable gate arrays, and SRAM Memory.
For this research, we propose to integrate the WUGS and the iiQueue to build a highly scalable ATM switch which supports per-virtual circuit QoS. A diagram of the combined system is shown above. Incoming cells would be processed and buffered by the iiQueue then forwarded to the WUGS switching fabric. By inserting the iiQueue between the Utopia interfaces of the line card and the IPP/OPP of the WUGS switch, no hardware modifications to either system would be required.
Integration of iiQueue and WUGS
A virtual circuit table is used to store each circuit's destination port(s), priority, queue length, and Quality of Service (QoS) parameters. This table, also implemented in RAM, is read and updated when cells enter and leave the system.
The 3DQ maintains service queues to sort connections by their virtual circuit, destination, and priority. Cell ordering is preserved by maintaining strict FIFO ordering of cells within a given virtual circuit. Head-of-line blocking is avoided by allowing cells destined for an uncongested port to bypass those cells destined for a congested port. Quality of Service is provided by using the priority level to determine the location of the connection within a service queue.
Photograph of the iiQueue
The iiQueue can process and buffer ATM cells at data rates up to 800 Mbps using a 25 MHz clock. It uses a 32-bit wide interface to attach to an ATM switch (left-most connectors of the PCB), and a programmable 8/16/32-bit wide interface to attach to a line card (right-most connectors of the PCB). The interfaces of the iiQueue and WUGS are compatible. They both have TTL-compatible signals and are designed to be used with a Utopia interface.
The logic for the system is implemented using two Xilinx XC4025-Epg299-2 FPGAs. One FPGA implements the ingress cell processing and controls input buffering, while the other implements the egress cell processing and controls the physical interface. The RAM for the system is implemented using four standard, 64-bit wide, CELP-socketed SRAM modules. Separate memory modules are used to implement the control memory, the cell buffer, and outgoing virtual circuit table.
As with the WUGS, the iiQueue communicates with a switch controller via control cells on preset VCIs. Control cells are sent to the 3DQ to create connections, tear down connections, and to modify QoS parameters. Detailed queueing statistics can be gathered by reading control cells from the iiQueue. QoS parameters and statistics include queue length, maximum queue length, connection priority, and cell loss counters. Additional parameters, such as an AAL5 frame counter, can be added by reprogramming the FPGA device and reserving space for an additional variable in control memory.
Understanding the equilibrium points of the entire system is critical in order to achieve guaranteed levels of Quality of Service and optimal switch usage. Using the hardware and software of the combined system, we propose to implement algorithms to support Available Bit Rate (ABR) traffic and provide dynamic traffic control. The processing of resource management cells can be handled by the reprogrammable logic of the iiQueue. Optimal values can only be achieved through interaction of the queue, the switch, and the controller.
We plan to connect the WUGS switch with the NCSA backbone network to measure application-level performance. During the course of an experiment (and only during an experiment), real traffic would be routed through the WUGS hardware. The performance of the applications would be measured as a function of background traffic and QoS parameters.
