Block diagram of WUGS with FPX modules
As shown in the diagram, the queuing modules are distributed across the inputs of the switch. Each queue maintains linked-list pointers in memory to track individual traffic flows. Pointers to each flow are then maintained both in a circuit table and in a service queue. The service queue tracks flows on a per-destination basis, allowing an input scheduler to achieve optimal throughput. The circuit index tracks cells on a flow basis, enabling flows to be served in response to an output port request.
By using a high-density Ball Grid Array (BGA) package,the new FPX consolidates the functions of the iiQueue's Ingress and Egress units into one FPGA. Two banks of 64-bit, Synchronous Dynamic Random Access Memory (SDRAM) provide pipelined cell storage. Two banks of 32-bit wide SRAM maintain pointers and data structures in the low-latency control memory. The circuit uses FIFO devices to separate the clock domain of the line card from that of the FPX.
PCB Layout of the new FPX Module
Physical configuration of FPX in WUGS module
Physically, this new FPX fits into the WUGS cabinet as shown above. The FPX (middle) attaches to the WUGS switch (bottom), as if it were a line card. The line card (top) then attaches to the FPX as if it were a switch. The height of the combined queue and line card easily fit within the cabinet. Because the new FPX is physically same size as a line card, every port of a WUGS could be equipped with a FPX module.
Design flow to reprogram the FPX Module
All memory signals attach to the FPGA. Because the function of the FPGA device is reprogrammable, the FPX can be implement arbitrary queue strategies. Further, the reprogrammable hardware allows rapid experimentation and testing of new designs. The design flow used to reprogram the FPGA is shown above. From our experience with the iiQueue, we expect the total time from a hardware modification to experimentation on the actual switch to be approximately fifteen minutes.
As a reprogrammable logic device with cell storage, there are several applications that can be implemented using a FPX. A few applicatons that have been already been proposed by other groups requesting FPX modules are:FPX performance for implementation of per-flow, fair-queue algorithms
Line
TypeLine
RateMemory operations
per cell period
(SRAM+SDRAM)Queuing
AlgorithmsOC3 155 Mbps 888 Operations WF2Q, SCFQ, LFVC, 3DQ, CORE OC12 622 Mbps 222 Operations SCFQ, LFVC, 3DQ, CORE OC48 2.4 Gbps 56 Operations 3DQ, CORE
If you or your group is interested in receiving FPX modules for your research, please take a minute to complete the survey form below: