| ECE291 |
Computer Engineering II |
J. W. Lockwood |
Lecture 15
Today's Topics
- STI: SeT Interrupt enable
Allow other routines to be serviced
- CLI: CLear Interrupt enable
Retain full control of CPU
- Latches incoming interrupt signals (IRQ signal)
- Allows masking interrupts (except NMI)
- Prioritizes Interrupts (IRQ 0==Highest)
- IF (interupt unmasked)
AND (interrupt flag=1)
AND (not servicing higher interrupt)
THEN call interrupt
- Consider the following ISRs for the Jarvic
2000 artificial heart
| Task |
Pri. |
Run
Time |
Dead-
line |
Event
Freq. |
Event
Period |
CPU
Load |
|---|
| BP | 1 | 1 ms | 3 ms | 100 Hz | 10 ms | 10% |
| OX | 2 | 5 ms | 20 ms | 50 Hz | 20 ms | 25% |
| PH | 2 | 10 ms | 20 ms | 10 Hz | 100 ms | 10% |
| VAG | 3 | 1 ms | 25 ms | 200 Hz | 5 ms | 20% |
- Calculate Worst-case delay
- Preemptive scheduling
Higher priority interrupt can interrupt
lower priority interrrupt.
- Non-Preemptive scheduling.
Interrupts run until they finish.
- Consider Asynchronous Events
- An event that is not strictly periodic
Example: Wireless ethernet controller - Packet can arrive at any time
- Visualize timing
Mention Lunar Lander
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