We have designed and implemented the first generation iPOINT ATM testbed . The testbed configured as a five-port input-buffered ATM switch system. It started fully functional in 1995, with an aggregate throughput of 800 Mb/s. I personally took charge of the design and development of the iPOINT Input Queue Module Sub-systems and the Trunk Port 1 Gb/s Queuing and Physical Link Interface Sub-system .
After building the first generation testbed successfully, I have been working on the design and development of an intelligent 3-Dimensional Queue (3DQ) system and a novel MUCS cell scheduler for the second-generation iPOINT ATM testbed which can be scaled to near Tb/s aggregate throughput.
The 3DQ avoids HOL blocking and
support comprehensive QoS functionality.
It is being prototyped using FPGA devices for core logic on
a 6-layer Printed-Circuit-Board (PCB).
The PCB measures 8"x14" and is loaded with
two 25K-gate FPGA chips for logic
and four industry-standard secondary-cache SRAM modules for cell
buffering memory.
While the current prototype is designed to process ATM cells at
622 Mb/s (OC-12).
The same 3DQ design could be used
to process cells at 2.5 Gb/s (OC-48)
with more aggressive circuit technology.
The MUCS cell scheduler, implementable by a low-cost semiconductor IC device, can resolve the output contention swiftly with high throughput cell transmission schedule which achieves near-100% link utilization.
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