Abstract

This paper presents the design and prototype of an intelligent, 3-Dimensional Queue (3DQ) system for high-performance, scalable, input buffered ATM switches. The 3DQ uses pointers and linked lists to organize ATM cells into multiple virtual queues according to priority, destination, and virtual connections, then selects proper cells for switching based on Quality-of-Service (QoS) parameters and run-time traffic conditions. Using Field-Programmable-Gate-Array (FPGA) devices, our prototype hardware can process ATM cells at 622 Mb/s (OC-12). Using more aggressive technology (Multi-Chip-Module (MCM) and fast GaAs logic), the same 3DQ design can process cells at 2.5 Gb/s (OC-48). Combined with the Matrix-Unit-Cell-Scheduler (MUCS) module, a high-performance input-buffered ATM switch system has been designed, which avoids Head-Of-Line (HOL) blocking and achieves near-100% link bandwidth utilization.

Keywords: 3DQ, QoS, multicast, input buffering, ATM switch, iPOINT testbed, MUCS, cell scheduler, computer network.

Areas of interest: B-ISDN and ATM, High Speed Network Trials, Quality of Service (QoS), Multicast Algorithms/Schemes.