iEDISON3 Publications

• WCANOPT: A. Dharchoudhury and S. M. Kang, Worst-case analysis and optimization of VLSI circuit performances, IEEE Trans. Comput. Aided Des., to appear in April 1995.
• USG: A. Dharchoudhury and S. M. Kang, User's guide to iEDISON3.0: A statistical design tool for VLSI circuits, Beckman Institute Technical Report UIUC-BI-VLSI-93-02, Univ. of Illinois at Urbana-Champaign, June 1993.
• VARMIN: A. Dharchoudhury and S. M. Kang, Performance-constrained worst-case variability minimization of VLSI circuits, Proc. ACM/IEEE Design Automation Conf., June 1993, pp. 154-158.
• WOROPT: A. Dharchoudhury and S. M. Kang, An integrated approach to worst-case design optimization of MOS analog circuits, Proc. ACM/IEEE Design Automation Conf., June 1992, pp. 704-709.